/*
 * Copyright 2022 Rich yang, 18158898020@189.com
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     https://www.apache.org/licenses/LICENSE-2.0
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied,
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 */

`timescale 1ns/1ps
`include "defines.v"
module openrv_min_sopc_tb;

  /* type declare */
  reg CLOCK_50MHZ;
  reg rst;

  initial begin
    CLOCK_50MHZ = 1'b0;
    forever #10 CLOCK_50MHZ = ~CLOCK_50MHZ;
  end

  initial begin
    rst = `RstEnable;
    #200 rst = `RstDisable;
    #10000 $stop;
  end

  openrv_min_sopc openrv_min_sopc0(
	  .clk(CLOCK_50MHZ),
	  .rst(rst)
  );


  initial begin
    $dumpfile("openrv_min_sopc.vcd");
    $dumpvars(0, openrv_min_sopc0);
    $dumpvars(0, rst);
  end
endmodule
